The present invention relates generally to data transfer circuits. Specifically, a method and apparatus are provided for maximizing the data transmission rate from a source data path to selected channels of a destination data path having a different width from the source data path.
Inefficiencies naturally occur when data from a source of one width is transmitted to a destination of a different width. If the data destination has a narrower width than the data source, each data cycle transmitting the data from the source to the destination will waste bits. Looking at circuit configuration 100 in FIG. 1, for example, the width of data source 102 is 16 bits, while the width of destination 104 is 4 bits. In a typical application, data source 102 and destination 104 may be registers for storing data. Thus, only 4 bits will be transmitted in one data cycle from source to destination, meaning that 12 bits are wasted, assuming that data bus 106 has a total capacity of 16 bits. A complete transfer of data from source 102 to destination 104 will therefore require four data cycles on bus 106, which is very inefficient since it requires four transmissions to the same destination.
Similarly, when the data destination is wider than the data source, the destination is typically mapped into multiple ports (addresses), with the data being sent in multiple cycles to the different ports, again resulting in wasted bits in each data transmission. Looking at the circuit configuration 200 in FIG. 2, for example, the width of data source 202 is 16 bits, while the width of each destination 204 and 206 is also 16 bits. However, the first destination address 204 requires only 8 bits of source data and the second destination address 206 also requires 8 bits of source data. Thus, the first data cycle transmits 8 bits of data from source 202 to the first destination address 204, wasting 8 bits of source data that could have been transmitted across 16-bit wide data bus 208. The second data cycle then transmits another 8 bits of data from source 202 to the second destination 206, again wasting 8 bits of source data that could have been transmitted on data bus 208. Thus, two data cycles are needed for the entire data transmission, though data bus 208 could have handled the contents of the entire data source 202 in only one data cycle.
The problem described above is of particular concern when testing integrated circuit chips. Integrated circuit chips customarily undergo exhaustive testing during the manufacture process prior to encapsulation in a package or use of the package on a circuit board in order to ensure reliable operation of the chip. The chip die undergoes functional and parametric testing in at least two different stages of the manufacturing process. At one stage, a semiconductor wafer containing multiple chip dies is probed by a probe tester that tests each of the dies individually. At another stage, after an individual chip die has been encapsulated in a package, a programmable package tester can be used to thoroughly test the integrated circuit chip package.
In a preferred digital test system, testing is controlled by a control unit, which may be, for example, a central processing unit (CPu) or a dedicated block of control logic. These test systems generally include a data source, usually a memory space divided into separate tester channels, for storing state information for each pin of the integrated circuit chip. The stored DUT input and output states are commonly referred to as test vectors. In order to perform a functional test of the device, the device tester, under control of appropriate test software, applies excitations to and receives responses from the device under test (DUT) under control of the tester. More specifically, the control unit transfers test vector data from the data source through the tester channels to a destination, the DUT pins. The control unit also transfers the test vector data from the data source to a comparator, where each resultant output state of the DUT is compared to an expected value by the tester. If the actual and expected values correspond, the chip has passed the test.
For example, the integrated circuit chip may be a programmable logic device (PLD), which is a programmable integrated circuit that allows the user of the circuit, using software control, to customize the logic functions the circuit will perform. In this example, a first group of test vectors is used to initialize the PLD in a desired logic configuration, and a second group of test vectors is then used to exercise the configured PLD. Again, the observed result is then compared with an expected result to see if the PLD is functioning properly.
In such test systems, the speed with which the control unit can move data from the data source to the DUT and comparators is of primary importance. The faster the control unit can move the data, the greater the resultant test vector rate. An exemplary alternate method of increasing the test vector rate is described in related application Ser. No. 08/790,693, entitled "METHOD AND APPARATUS OF INCREASING THE VECTOR RATE OF A DIGITAL TEST SYSTEM," also assigned to the assignee of the present application and incorporated by reference herein. Therefore, the inefficient transmission of data from a source of one width to a destination of a different width described above seriously impairs the speed with which the control unit can execute a test program. The multiple data cycles required to transfer data from source to destination slow down the test program and lengthen the testing process.
Therefore, a new testing method and apparatus are desired to maximize the data transmission rate from a source data path to selected channels of a destination data path having a different width from the source data path, especially in the context of an integrated circuit chip test system.